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How-to Articles |
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Measurement Brief: D.C. Blocks, a Trap for the Unwary when Using Long Patterns D.C. blocks are a common component used during testing, and their characteristics are not always taken into consideration. This paper showcases what can happen to signal integrity if the wrong D.C. block is chosen in a test setup … Read more |
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Great Resources |
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• A Trio of Jitter White Papers |
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*NEW*
BERTScope Jitter Map Comparison Study As with any new product capable of jitter decomposition, one may wonder how it compares to existing jitter measurement products. This paper provides an in-depth comparison of Jitter Map performance to that of the DCA-J sampling oscilloscope … Read more
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Why Do Different Instruments Give Different Jitter Answers? Signal integrity engineers complain that every high speed instrument in their lab gives a different answer when measuring jitter. Here we look at some reasons why … Read more
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Jitter Map "Under the Hood" – A New Methodology for Jitter Separation Jitter Map, an innovative new capability on the BERTScope, bridges the gap between sophisticated jitter component analysis using oscilloscopes and the confidence of deep, BER-based total jitter measurements … Read more |
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What's New at SyntheSys?
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DisplayPort Sink and Source Compliance Testing The BERTScope DisplayPort solution is certified for DisplayPort Sink and Source testing to CTS (Compliance Test Specification) 1.1, with fully automated software for Sink testing – compliance made easy … Read more |
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Come and See Us at... |
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Webcast: Characterizing an SFP+ Transceiver at the 16G Fibre Channel Rate
10 am PST/1 pm EST October 15, 2009
In association with Tektronix
See how an SFP+ Transceiver can be characterized at the 16G Fibre Channel rate of 14.025 Gb/s with the help of the BERTScope Si 17500C and BERTScope CR 14300A.
Webcast sponsored by Lightwave
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PCI-SIG Compliance Workshop #69
Taipei, Taiwan
 October 12 – 16, 2009
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USB 3.0 Compliance Workshop #70
Portland, Oregon November 2-5, 2009
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VESA DisplayPort Plug Test
Yokohama, Japan December 7-10, 2009
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Question:
How do I get a SATA Host into loopback?
Answer:
There are two ways to get a SATA host into loopback for physical
layer testing with a BERTScope.
The first method uses a tool such as the ULINK DriveMaster
software or a protocol analyzer to generate the proper bit sequence to get the
SATA host into BIST (built-in self test) mode. With the help of the
SATA tee (which enables a smooth transition to the
BERTScope for devices that do not support a disconnection from the protocol
generator), the BERTScope can then drive the compliance data pattern for
SATA host testing.
The second method uses the new BIST initiation patterns
available now from the
BERTScope website. These patterns are capable of getting a
host device into loopback using only the Pattern Generator in the BERTScope.
BIST initiation patterns are available for the 1.5, 3, and 6 Gb/s SATA data rates. |
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