BERTScope Si 26 / 17.5 / 8.5 Gb/s
Analyzer with Stressed Eye
The BERTScope Si 8500C, 17500C, and 25000C Signal Integrity Analyzers advance the BERTScope Family to 8.5, 17.5, and 26 Gb/s, respectively. Covering serial data interfaces from 1 Gb Ethernet to future 16x Fibre Channel and 4x 25.78 Gb/s 100 Gb Ethernet, the appropriate model BERTScope Si reduces your time to market by providing the most advanced and comprehensive combination of signal integrity analysis and test tools available in a single instrument.
The BERTScope Si features enhanced integrated stress generation, extensive analysis tools such as deep BER-based BER Contour eye opening display and measurement, and optional Jitter Map with PRBS-31 jitter decomposition. With the BERTScope’s easy-to-use interface, you will spend less time on the learning curve, and more time troubleshooting your signal integrity problems.
New to the Si Family are two options:
Symbol Filtering:
With the Symbol Filtering Software Option (included on the 8500C), the BERTScope can perform asynchronous BER and Jitter Tolerance testing on 8b/10b encoded systems such as USB 3.0, making receiver compliance testing simple and straightforward.
Stressed Live Data:
The BERTScope Stressed Live Data Software Option enables engineers to add various types of stress to real data traffic in order to stress devices with bit sequences representative of the environment they will encounter once deployed. Using live traffic with added stress tests the boundaries of device performance and lends added confidence to designs before they are shipped.
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Key Features of the BERTScope C Models: |
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- Symbol Filtering option (included on the 8500C) enables asynchronous BER testing:
- User-specified clock compensation symbols such as SKPs in USB 3.0 or ALIGNs in SATA are automatically filtered from the incoming data for proper synchronization.
- Count of filtered bits is maintained for accurate BER measurement.
- Stressed Live Data option supports data rates up to the maximum of the BERTScope:
- Adds calibrated stress including sinusoidal jitter (SJ), random jitter (RJ), bounded uncorrelated jitter (BUJ), sinusoidal interference (SI), F/2 jitter, and spread spectrum clocking (SSC) to live data traffic.
- Line cards and network equipment can be tested with stressed live traffic, the only way to know for sure that there aren’t problems arising at network interfaces.
- Optional BERTScope Jitter Map creates the first instrument to provide deep BER-based detailed jitter decomposition. Jitter Map starts with the "gold standard" of deep BER measurement-based dual-Dirac TJ, and then leverages its ability to lock onto a data pattern in order to provide additional insight into jitter components including:
- BUJ, data dependent jitter (DDJ), inter-symbol interference (ISI), duty cycle distortion (DCD), and sub-rate jitter* (SRJ), including F/2 jitter*
- Accurate deterministic jitter (DJ) and random jitter (RJ)
- Jitter decomposition on patterns up to
PRBS-23 and PRBS-31, using Jitter Triangulation
- Automated data dependent pulse width shrinkage (DDPWS) measurement for 8xFC, SFP+, and future 100 GbE
- Optional CleanEye automated eye diagram FIR equalization tap setting optimization**
- De-embed the effect of cables and adapters on the device under test
- Also works with customer-provided S21 channel data
tap values
- The BERTScope Si also features enhanced integrated stress generation:
- Increased maximum available sinusoidal jitter (SJ) amplitudes
exceed the jitter tolerance
requirements of existing standards including SDH, SONET, OTN, XAUI, 10GbE, OIF-CEI, SATA,
SAS, and Fibre Channel
- The BERTScope Si 25000C covers 100GBASE-LR4 and -ER4 jitter tolerance
requirements, with room for margin testing
- F/2 jitter***, which varies odd
versus even bit width
- SSC is available for data rates up to 8.5 Gbs (Si 8500C), 17.5 Gb/s
(Si 17500C), or 26 Gb/s (Si 25000C) and may be
used simultaneously with SJ and other jitter sources
- Rear panel reference clocks input and output frequencies are 10 MHz, 100 MHz,
106.25 MHz, 133.33 MHz, 156.25 MHz, and 200 MHz
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Key Features of the BERTScope Stressed Analyzers: |
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- Pattern Generation and Error Analysis
- Patented Error Location Analysis™
- Comprehensive range of differential divided clock outputs
for supplying test devices with an instrument grade clock
- External clock input upgraded to allow imposition
of stress
- Variable depth eye and mask measurements, to allow
correlation with shallow sampling scope measurements or a deeper, more revealing
view of device performance
- Jitter tolerance compliance template testing with
margin testing
- High Speed BER Measurements
- Integrated, Calibrated Stress Generation
- Sinusoidal Jitter to 80 MHz
- Random Jitter†
- Bounded, Uncorrelated Jitter†
- Sinusoidal Interference
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- Electrical Stressed Eye Testing for:
- XFP/XFI
- OIF/CEI
- Fibre Channel
- Serial ATA I/O
- USB 3.0
- etc.
- Optical Stressed Eye Testing for:
- 100 GbE (4x 25.78 Gb/s) with BERTScope Si 25000C
- 10 GbE
- 1, 2, 4, 8x Fibre Channel
- 1 GbE
- Integrated eye diagram analysis with
BER correlation
- Physical layer test suite with Mask Testing, Jitter
Peak, BER Contour, and
Q-Factor Analysis
- Compliant Contour test for Mask Performance Evaluation
to BER 10-12, as called for by latest
standards including XFP/XFI and OIF-CEI
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The BERTScope Analyzer Family
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